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  advanced information is43lr16800e 1 2m x 16bits x 4banks mobile ddr sdram description the is43lr16800e is 134,217,728 bits cmos mobi le double data rate synchronous dram or ganized as 4 banks of 2,097,152 words x 16 bits. this product uses a double-data-rate architecture to achieve high-speed operatio n. the address lines are multiplexed with the data input/ output signals on a multiplexed x 16 input/ output bus. the double data rate architecture is essentially a 2 n prefetch architecture with an interface designed to transfer two data wo rds per clock cycle at the i/o pins. this product offers fully sync hronous operations referenced to both rising and falling edges of the cl ock. the data paths are internally pipelined and 2n-bits prefetche dto achieve very high bandwidth. all input and output vo ltage levels are compatible with lvcmos. features ? jedec standard 1.8v power supply. ? vdd = 1.8v, vddq = 1.8v ? four internal banks for concurrent operation ? mrs cycle with address key programs - cas latency 2, 3 (clock) - burst length (2, 4, 8, 16) - burst type (sequential & interleave) ? fully differential clock inputs (ck, /ck) ? all inputs except data & dm are sampled at the rising edge of the system clock ? data i/o transaction on both edges of data strobe ? bidirectional data strobe per byte of data (dqs) ? dm for write masking only ? edge aligned data & data strobe output ? center aligned data & data strobe input ? 64ms refresh period (4k cycle) ?auto & s el f refres h ? concurrent auto precharge ? maximum clock frequency up to 166mhz ? maximum data rate up to 333mbps/pin ? special power saving supports. - pasr (partial array self refresh) - auto tcsr (temperature compensated self refresh) - deep power down mode - programmable driver strength control by full strength or 1/2, 1/4, 1/8 of full strength ? lvcmos compatible inputs/outputs ? 60-ball fbga package copyright ? 2009 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specif ication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, produ cts or services described herein. customers are advised to obtain the latest version of this device specification before relying on any publish ed information and before placing orders for products.
advanced information is43lr16800e 2 figure1: 60ball fbga ball assignment a b c d e f g h j k 1 2 3 4 5 6 7 8 9 vss dq15 vssq vddq dq13 dq14 vssq dq11 dq12 vddq dq9 dq10 vss udm nc cke ck /ck a9 a11 nc a6 a7 a8 vss a4 a5 vddq dq0 vdd dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq nc ldm vdd /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 vdd vssq udqs dq8 dq7 ldqs vddq [top view]
advanced information is43lr16800e 3 table2 : pin descriptions symbol type function descriptions ck, /ck input system clock the system clock input. ck and /ck are differential clock inputs. all address and control in put signals are registered on the crossing of the rising edge of ck and falling edge of /ck. input and output data is referenced to the crossing of ck and /ck. cke input clock enable cke is clock enable controls input. cke high activates, and cke low deactivates internal cl ock signals, and device input buffers and output drivers. cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. /cs input chip select /cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when /cs is registered high. /cs provides for external bank selection on systems with multiple banks. /cs is considered part of the command code. ba0, ba1 input bank address ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register (standard mode register or extended mode register) is loaded during a load mode register command. a0~a11 input address row address : ra0~ra11 column address : ca0~ca8 auto precharge : a10 /ras, /cas, /we input row address strobe, column address strobe, write enable /ras, /cas and /we define the operation. refer function truth table for details. ldm, udm input data input mask dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only. dq0~dq15 in/output data input/output multiplexed data input/output pin. ldqs, udqs in/output data input/output strobe output with read data, input with write data. dqs is edge- aligned with read data, centered in write data. data strobe is used to capture data. vdd supply power supply power supply vss supply ground ground vddq supply dq power supply power supply for dq vssq supply dq ground ground for dq nc nc no connection no connection.
advanced information is43lr16800e 4 figure2 : functional block diagram extended mode register self refresh logic & timer internal row counter row pre decoder column pre decoder column add counter address register mode register data out control burst counter a d dress buffer s state ma c h i n e row deco d e rs row decod e rs row deco d e rs row deco d e rs 2m x16 b a n k 1 2m x16 b a n k 0 mem or y cell array colu m n de coder s 2m x16 b a n k 2 2m x16 b a n k 3 wr ite data r e gis t er 2- bi t p r ef etch uni t sense am p &i/ o gate outp ut b uffer & l og i c dq0 . . . . . . . dq15 data strob e transm i t t e r data strob e receiver input buf f e r & logic | | 16 | | | | 32 | | ds udqs,ldqs ds x16 x32 pasr row a c ti ve ref r esh colu m n active bank select bu rs t len g t h ca s lat e ncy --------- a0 a1 a11 ba0 ba1 ldm/udm /w e /cas /ras /cs ck e ck /ck
advanced information is43lr16800e 5 figure3 : simplified state diagram power on precharge all banks mrs emrs active power down deep power down idle all banks precharged s elf refresh auto refresh row active precharge preall write write a read read a burst stop precharge power down dpds power applied dpdsx mrs refa refsx refs act ckeh ckel pre ckel ckeh write read bst pre pre pre write a write read read a read write a read a automatic sequence act = active bst = burst ckel = enter power- down ckeh = exit power-down dpds = enter deep power-down dpdsx = exit deep power- down emrs = ext. mode reg. set mrs = mode register set pre = precharge preall= precharge all banks refa = auto refresh refs = enter self refresh refsx = exit self refresh read = read w/o auto precharge read a = read with auto precharge write = write w/o auto precharge write a = write with auto precharge
advanced information is43lr16800e 6 burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type a nd is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 3. m3 burst type 0 sequential 1 interleave m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved m2 m1 m0 burst length m3 = 0 m3 = 1 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 16 16 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved address bus a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 figure4 : mode register set (mrs) definition ba0 ba1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 cas latency bt burst length note: m13(ba1) and m12(ba0) must be set to ?0? to select mode register (vs. the extended mode register) mode register (mx)
advanced information is43lr16800e 7 table3 : burst definition burst length starting column address order of access within a burst a3 a2 a1 a0 sequential mode interleave mode 2 x x x 0 0-1 0-1 x x x 1 1-0 1-0 4 x x 0 0 0-1-2-3 0-1-2-3 x x 0 1 1-2-3-0 1-0-3-2 x x 1 0 2-3-0-1 2-3-0-1 x x 1 1 3-0-1-2 3-2-1-0 8 x 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 x 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 x 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 x 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 x 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 x 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 x 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 x 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 16 0 0 0 0 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0 0 0 1 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14 0 0 1 0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13 0 0 1 1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12 0 1 0 0 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11 0 1 0 1 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10 0 1 1 0 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9 0 1 1 1 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8 1 0 0 0 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 1 0 0 1 9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8 9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6 1 0 1 0 10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9 10-11-8-9-14-15-12-13-2-3-0-1-6-7-4-5 1 0 1 1 11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10 11-10-9-8-15-14-13-12-3-2-1-0-7-6-5-4 1 1 0 0 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 12-13-14-15-8-9-10-11-4-5-6-7-0-1-2-3 1 1 0 1 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 13-12-15-14-9-8-11-10-5-4-7-6-1-0-3-2 1 1 1 0 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-12-13-10-11-8-9-6-7-4-5-2-3-0-1 1 1 1 1 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-14-13-12-11-10-9-8-7-6-5-4-3-2-1-0 note : 1. for a burst length of two, a1-a8 select the block of two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2-a8 select the block of four burst; a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a8 select the block of eight burst; a0-a2 select the starting column within the block. 4. for a burst length of sixteen, a4-a8 select the block of eight burst; a0-a3 select the starting column within the block. 5. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block.
advanced information is43lr16800e 8 figure5 : extended mode set (emrs) register address bus extended mode register (ex) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 e2 e1 e0 self refresh coverage 0 0 0 four banks 0 0 1 two bank (ba1=0) 0 1 0 one bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 one eighth of total bank (ba1 = ba0 = row address msb=0) 1 1 0 one sixteenth of total bank (ba1 = ba0 = row address 2 msbs=0) 1 1 1 reserved e6 e5 driver strength 0 0 full strength 0 1 1/2 strength 1 0 1/4 strength 1 1 1/8 strength ba0 ba1 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 ds 0 0 pasr note: e13(ba1) and e12(ba0) must be set to ?1,0? to select extend mode register (vs. the base mode register)
advanced information is43lr16800e 9 the 128mb mobile ddr sdram is a high-speed cmos, dynamic random -access memory containing 134,271,728-bits. it is internally configured as a quad-bank dram. the 128mb mo bile ddr sdram uses a double data rate ar chitecture to achieve high speed operatio n. the double data rate architecture is esse ntially a 2n-prefetch architecture, with an interface designed to transfer two data wo rds per clock cycle at the i/o balls, single read or write access for the 128mb mobile ddr sdram consists of a single 2n-bit wide, one-clock- cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o balls. read and write accesses to the mobile ddr sdram are burst orient ed; accesses start at a selected location and continue for a pr ogrammed number of locations in a programmed sequence . accesses begin with the re gistration of an active command, which is then followe dby a read or write command. the address bits registered coincident wi th the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the ad dress bits registered coincident with the read or write comman d are used to select the starting column location for the burst access. it should be noted that the dll signal that is typically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to normal operation, the mobile ddr sdram must be powere d up and initialized. the following sections provide detailed inf ormation covering device initialization, register definition, command desc riptions and device operation. power up and initialization mobile ddr sdram must be powered up and initialized in a predefin ed manner. power must be applied to vdd and vddq (simultaneous ly). after power up, an initial pause of 200 usec is required. and a precharge all command will be issued to the mobile ddr. then, 2 or more auto refresh cycles will be provided. after the auto refresh cycl es are completed, a mode register set(mrs) command will be iss ued to program the specific mode of operation (cas latency, burst leng th, etc.) and a extended mode register set(emrs) command will be issued to partial array self refresh(pasr). the following these cycles, the mobile ddr sdram is ready for normal operation. to ensure d evice functionality, there is a predefined sequence that must occur at device power up or if there is any interruption of device power . to properly initialize the mobile ddr sdram, this sequence must be followed: 1. to prevent device latch-up, it is reco mmended the core power (vdd) and i/o power (vddq) be from the same power source and br ought up simultaneously. if separate power sources are used, vdd must lead vddq. 2. once power supply voltages are stable and the cke ha s been driven high, it is safe to apply the clock. 3. once the clock is stable, a 200 s (minimum) delay is required by the mobile ddr sdram prior to applying an executable command. during this time, nop or deselect comman ds must be issued on the command bus. 4. issue a precharge all command. 5. issue nop or deselect commands for at least trp time. 6. issue an auto refresh command followed by nop or deselect commands for at least trfc time. issue a second auto refresh command followed by nop or deselect commands for at least trfc ti me. as part of the individualization sequence, two auto refresh commands must be issued. typically, both of these co mmands are issued at this stage as described above. 7. using the load mode register command, lo ad the standard mode register as desired. 8. issue nop or deselect commands for at least tmrd time. 9. using the load mode register command, load the extended mode register to the desired operatin g modes. note that the order in which the standard and extended mode re gisters are programmed is not critical. 10. issue nop or deselect commands for at least tmrd time. 11. the mobile ddr sdram has been properly initia lized and is ready to receive any valid command. functional description
advanced information is43lr16800e 10 notes: 1. pcg = precharge command, mrs = load mode regi ster command, aref = autorefresh command, act = active command, ra = row address, ba = bank address. 2. nop or deselect commands are required for at least 200 s. 3. other valid commands are possible. 4. nops or deselects are required during this time. figure6 : power up sequence act ba ba 0 = l , ba 1 = h ba 0 = l , ba 1 = l all banks mrs mrs ar ef ar ef pcg nop nop 2 nop 3 c l k / c l k cke t 0 c ommand 1 t 1 ta 0 t c h tcl dm a 0 ~ a 9 , a 11 tb 0 tc 0 td 0 te 0 tf 0 tck lvcmos high level a 10 ba 0 , ba 1 dqs , dq high - z t = 200 s tis ra code code tis tih ra code code tis tih tis tih trp 4 trfc 4 trfc 4 tmrd 4 tmrd 4 tih vddq vdd tis tih load standard mode register load extended mode register power - up : vdd and c l k stable don ? t care
advanced information is43lr16800e 11 mode register the mode register is used to define the sp ecific mode of operation of the mobile ddr sdram. this definition includes the select ion of a burst length, a burst type, a cas latency. th e mode register is programmed via the load mode register command and will retain t he stored information until programmed again, the device goes into deep power-down mode, or the device loses power. mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or interleaved), a4-a6 specify th e cas latency, and a7-a11 should be set to zero. ba0 and ba 1 must be zero to access the mode register. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length being programmable, as shown in figur e (mode register set definition). the burst length determines the maximum number of column locations that can be accessed for a g iven read or write command. burst lengths of 2, 4,8 or 16 are av ailable for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or inco mpatibility with future versions may result. when a read or wri te command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a bo undary is reached. the block is uniquely selected by a1-a8 when the burst length is set to two; by a2-a8 when the burst length is set to four; by a3-a8 when the burst length is set to eight; and by a4- a8 when the burst length is set to sixteen. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. cas latency the cas latency is the delay, in clock cycl es, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2, 3 clocks, as show n in figure (standard mode register definition). for cl = 3, if the read command is registered at clock edge n, then the data will be available at (n + 2 clocks + tac). for cl =2, if the read command is registered at clock edge n, then the data will be available at (n + 1 clock + tac). figure7 : cas latency (bl=4) / c k c k c ommand t 0 t 1 t 2 t 3 t 1 n t 2 n t 3 n read nop nop nop dqs dq tac cl = 3 d out n + 1 trpre 2 tck t 4 t 4 n nop trpst d out n d out n + 2 d out n + 3 don ? t care dqs dq tac cl = 2 d out n + 1 trpre 1 tck trpst d out n d out n + 2 d out n + 3 l l
advanced information is43lr16800e 12 extended mode register the extended mode register controls the f unctions beyond those controlled by the mode register. these addi tional functions are special features of the mobile ddr sdram. they include partia l array self refresh (pasr) and driver strength (ds). the extended mode register is programmed via the mode register set command (ba0=0, ba1=1) and retains the stored information un til programmed again, the device goes into deep power-down mode, or the device loses power. the extended mode register must be programmed with a7 through a 11 set to ?0?. the extended mode register must be loaded when al l banks are idle and no bursts are in progress, and the controller m ust wait the specified time befo re initiating any subsequent o peration. violating either of these requirements results in unspecified operation. partial array self refresh for further power savings during self refresh, the pasr feature allo ws the controller to select the amount of memory that will b e refreshed during self refresh. th e refresh options are as follows: ? full array: banks 0, 1, 2, and 3 ? half array: banks 0 and 1 ? quarter array: bank 0 ? one eight array: half of bank 0 ? one sixteen array: quarter of bank 0 write and read commands can still occur during standard operation, but only the selected banks will be refreshed during self re fresh. data in banks that are disabled will be lost. output driver strength because the mobile ddr sdram is designed fo r use in smaller systems that are mostly point to point, an option to control the dr ive strength of the output buffers is available. drive strength shou ld be selected based on the expe cted loading of the memory bus .bits a5 and a6 of the extended mode register can be used to select the driver strength of the dq outputs. there are four allowable settings for the output drivers. temperature compensated self refresh in the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device . temperature compensated self refresh allows the controller to pr ogram the refresh interval during self refresh mode, according to the case temperature of the mobile sdram device . this allows great power savings during se lf refresh during most operating temperat ure ranges. only during extreme temperatures would the controller have to select a tcsr level that will guarantee data during self refresh. every cell in the dram requires refreshing due to the capacitor l osing its charge over time. the refresh rate is dependent on te mperature. at higher temperatures a capacitor loses ch arge quicker than at lower temperatures, re quiring the cells to be refreshed more of ten. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range exp ected. thus, during ambient temperatures, the power consumed during re fresh was unnecessarily high, because the refresh rate was set t o accommodate the higher temperatures. this temperature compensated refresh rate will save powe r when the dram is operating at normal temperatures.
advanced information is43lr16800e 13 commands the following commands truth table and dm operation truth table pr ovide quick reference of available commands. this is followe dby a written description of each command. deselect the deselect function (/cs high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perfor m a nop (/cs = low, /ras = /cas = /we = high). this prevents unwanted commands from be ing registered during idle or wait states . operations already in progress are not a ffected. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 i nputs selects the bank, and the address provided on inputs a0?a11 select s the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command mu st be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, an d the address provided on inputs a0?a8 selects the starting column loca tion. the value on input a10 determines whether or not auto prech arge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, a nd the address provided on inputs a0-a8 selects the starting column loca tion. the value on input a10 determines whether or not auto prech arge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subje ct to the dm input logic level appearing coincident with the data. if a give n dm signal is registered low, the corresponding data will be w ritten to memory; if the dm signal is registered hi gh, the corresponding data inputs will be ig nored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a pa rticular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (trp) after the precharge command is issued . except in the case of concurrent auto p recharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current b ank and does not violate any other timing parameters. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1select the ba nk. otherwise ba0, ba1 are treated as ?don?t care.? once a bank h as been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precha rge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in t he process of precharging.
advanced information is43lr16800e 14 auto precharge auto precharge is a feature which performs the same individual-b ank precharge function described above, but without requiring a n explicit command. this is accomplished by using a10 to enable auto precha rge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or wr ite command is automatically performed upon completion of the re ad or write burst. auto precharge is nonpersistent in that it is eith er enabled or disabled for each individual read or write comman d. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is init iated at the earliest valid stage within a burst. this ?earliest valid stage? is det ermined as if an explicit precharge command was issued at th e earliest possible time, without violating tras (min). the user must not issue anot her command to the same bank until the precharge time (trp) is completed. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated. th e open page which the read burst was terminated from remains open. auto refresh auto refresh is used during normal operation of the mobile ddr sdram and is analogous to /cas-before-/ras (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issu ed each time a refresh is required. the addressing is generate dby the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh co mmand. the 128mb mobile ddr s dram requires auto refresh cycles at an average interval of 15.6 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refre sh period. the auto refresh period begins wh en the auto refresh command is registered and ends trfc later. self refresh the self refresh command can be used to reta in data in the mobile ddr sdram, even if the rest of the system is powered down. w hen in the self refresh mode, the mobile ddr sdram retains data with out external clocking. the self refresh command is initiated li ke an auto refresh command except cke is disabled (low). all command and address input sign als except cke are ?don?t care? during sel f refresh. during self refresh, the device is refreshe d as identified in the external mode regist er (see pasr setting). for a the full arr ay refresh, all four banks are refreshed simultaneously with the refresh frequenc y set by an internal self refresh oscillator. this oscillator changes due to the temperature sensors input. as the case temperature of the mobile ddr sdra m increases, the oscillation frequency will chang eto accommodate the change of temperature. this happens because the d ram capacitors lose charge faster at higher temperatures. to e nsure efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data. the procedure for exiting self refr esh requires a sequence of commands. first, cl ock must be stable prior to cke going back hig h. once cke is high, the mobile ddr sdram must have nop commands issued fo r txsr is required for the completion of any internal refresh in progress. deep power-down deep power down is an operating mode to achieve maximum power re duction by eliminating the power of the whole memory array of t he devices. data will not be retained once the device enters deep power down mode. this mode is entered by having all banks id le then /cs and /we held low with /ras and /cas held high at the rising edge of the clock, while cke is low. this mode is exited by asserting cke high.
advanced information is43lr16800e 15 note: 1. all states and sequences no t shown are illegal or reserved. 2. deslect and nop are func tionally interchangeable. 3. autoprecharge is non-persistent. a10 high enables autoprecharge, while a10 lo w disables autoprecharge 4. burst terminate applies to only read bursts with autoprecharge disabled. this command is undefined and should not be used for read with autoprecharge enab led, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged. if a10 is high, all banks are precharged and ba0-ba1 a re don?t care. 7. this command is auto refresh if cke is high, and self refresh if cke is low. 8. all address inputs and i/o are ''don't care'' except for ck e. internal refresh counters control bank and row addressing. 9. all banks must be precharged before issuing an auto-refresh or self refresh command. 10. ba0 and ba1 value select between mrs and emrs. 11. used to mask write data, provided coincident with the corresponding data. 12. cke is high for all commands shown except self refresh and deep power-down. f u nct io n /c s /ras /ca s /we ba a1 0/a p addr no t e deselect (nop ) h x x x x x x 2 no op era t ion ( n op ) l h h h x x x 2 a c tiv e ( s elect bank an d ac tiv a te row) l l h h v row row read (selec t bank a n d colum n a n d s tart read burs t) l h l h v l col read with ap (r e ad bur s t w i th au to recharge) l h l h v h col 3 write (selec t ba nk a n d colum n a n d s t art wri te b u rs t) l h l l v l col write w i th ap (wri te bu rst w i th au t o recharge) l h l l v h col 3 bur s t term ina t e or enter deep p o wer down l h h l x x x 4,5 p rech a rge (d eac t ivat e r o w in selec t ed ban k ) l l h l v l x 6 p rech a rge al l (deactiv ate row s in all banks) l l h l x h x 6 au to ref r esh o r enter self re f r esh l l l h x x x 7,8,9 mode register set l l l l v op_code 10 f u nct io n dm dq no t e wr ite en able l va l id 11 w r i t e inhi bi t h x 11 table 5 : dm trut h table table 4: c o mmand truth table
advanced information is43lr16800e 16 note: 1. cken is the logic stat e of cke at clock edge n ; cke n -1 was the state of cke at the previous clock edge. 2. current state is the state of mobile ddr immediately prior to clock edge n . 3. commandn is the command regist ered at clock edge n, and action n is the result of command n . 4. all states and sequences no t shown are illegal or reserved. 5. deselect and nop are functionally interchangeable. 6. power down exit time (txp) should elapse before a command other than nop or deselect is issued. 7. self refresh exit time (txsr) should elapse befo re a command other than nop or deselect is issued. 8. the deep power-down exit procedure must be followed as discussed in the deep powe r-down section of the functional description . 9. the clock must toggle at least one time during the txp period. 10. the clock must toggle at least once during the txsr time. see the other truth tables h h enter deep power down burst terminate all banks idle l h self refresh entry auto refresh all banks idle l h 5 active power down entry nop or deselect bank(s) active l h 5 precharge power down entry nop or deselect all banks idle l h 5,8 exit deep power down nop or deselect deep power down h l 5,7,10 exit self refresh nop or deselect self refresh h l 5,6,9 exit power down nop or deselect power down h l maintain deep power down x deep power down l l maintain self refresh x self refresh l l maintain power down x power down l l no t e ac tion n comman d n cur rent sta t e cken cken-1 table 6 : cke trut h table
advanced information is43lr16800e 17 note: 1. the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences no t shown are illegal or reserved. 4. this command may or may not be bank specific. if all banks ar e being precharged, they must be in a valid state for prechargi ng. 5. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 6. the new read or write command could be auto precharge enabled or auto precharge disabled. 7. current state definitions: idle: the bank has been prec harged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharg e disabled, and has not yet terminated or been terminated. 8. the following states must not be interrupted by a command issued to the same bank. deselect or nop commands or allowable commands to the other ba nk should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table3, and according to truth table 4. ? precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. ? row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be in the ''row active'' state. ? read with ap enabled: starts with the registration of the read command with auto precharg e enabled and ends when trp has been met. once trp has been met, the bank will be in the idle state. ? write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. table7 : current state bank n truth table (command to bank n ) cur rent sta t e c o mmand act io n no t e /c s /ras /ca s /we des c ription any h x x x deselect(nop ) c o n t inue pr e v ious o p e r ation l h h h nop c o n t inue pr e v ious o p e r ation idl e l l h h act i ve selec t an d ac ti vat e r o w l l l h auto refresh aut o refr e s h 10 l l l l m o de register set m o de regist er set 10 l l h h pr e c har g e n o a ct i o n if b a n k i s id l e row a c ti ve l h l h read selec t colum n & s tart read bu rs t l h l l write selec t colum n & s tart wri te bu rs t l l h l pr e c har g e d e acti vate r o w in bank (o r banks) 4 read (wi t hou t a u t o re ch arge ) l h l h read truncate r e ad & start ne w r e ad burst 5,6 l h l l write truncate r e ad & start ne w wr ite burst 5,6,13 l l h l pr e c har g e truncate r e ad, start pre c harge l h h l bur s t term ina te bu rs t term inate 11 wr ite (wi t hou t a u t o precharge) l h l h read truncate wr ite & start ne w r e ad burst 5,6,12 l h l l write trun cate wr ite & start n e w wr ite burst 5,6 l l h l pr e c har g e trun cate wr ite, start pre c h a rge 12
advanced information is43lr16800e 18 9. the following states must not be interrupted by any executab le command; deselect or nop commands must be applied to each positive clock edge during these states. ? refreshing: starts with registration of an auto refresh command and ends when trfc is met. once trfc is met, the mobile ddr will be in an ''all banks idle'' state. ? accessing mode register: starts with registration of a mode register set co mmand and ends when tmrd has been met. once tmrd is met, the mobile ddr will be in an ''all banks idle'' state. ? precharging all: starts with the registration of a precharge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 10. not bank-specific; requires that all bank s are idle and no bursts are in progress. 11. not bank-specific. burst terminate affects the most recent read burst, regardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write command.
advanced information is43lr16800e 19 table8 : current state bank n truth table (command to bank m ) cur rent sta t e c o mmand act io n no t e /c s /ras /ca s /we des c ription any h x x x deselect(nop ) c o n t inue pr e v ious o p e r ation l h h h nop c o n t inue pr e v ious o p e r ation idl e x x x x any any co m m a nd all o w e d t o bank m row a c ti vatin g, ac ti ve, or pre c h a rg i n g l l h h act i ve ac ti vate r o w l h l h read start read burst 8 l h l l write start write burs t 8 l l h l pr e c har g e pre c h a rg e read w i th aut o precha rge d isabled l l h h act i ve ac ti vate r o w l h l h read state read burst 8 l h l l write start write burs t 8,10 l l h l pr e c har g e pre c h a rg e wri t e w i th auto precharge d isabled l l h h act i ve ac ti vate r o w l h l h read start read burst 8,9 l h l l write start write burs t 8 l l h l pr e c har g e pre c h a rg e read w i th aut o pre c h a rg e l l h h act i ve ac ti vate r o w l h l h read start read burst 5,8 l h l l write start write burs t 5,8,10 l l h l pr e c har g e pre c h a rg e wri t e w i th auto precharge l l h h act i ve ac ti vate r o w l h l h read start read burst 5,8 l h l l write start write burs t 5,8 l l h l pr e c har g e pre c h a rg e
advanced information is43lr16800e 20 note: 1. the table applies when both cke n -1 and cke n are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences no t shown are illegal or reserved. 4. current state definitions: idle: the bank has been prec harged, and trp has been met. row active: a row in the bank has been activated, and trcd has b een met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharg e disabled, and has not yet terminated or been terminated. 5. read with ap enabled and writ e with ap enabled: the read with autoprecharge ena bled or write with autoprecharge enabled states can be broken into two parts: the access pe riod and the precharge period. for read with ap, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with auto precharge, the precha rge period begins when twr ends, with twr measured as if auto precharge was disabled. the access period starts with registration of the comm and and ends where the precharge period (or trp) begins. during the precharge period, of the read with autoprecharge e nabled or write with autoprecharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other banks may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided). 6. auto refresh, self refr esh, and mode register set commands may only be issued when all bank are idle. 7. a burst terminate command cannot be issued to another bank; it applies to the bank represen ted by the current state only. 8. reads or writes listed in the command column include read s and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. requires appropriate dm masking. 10. a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command.
advanced information is43lr16800e 21 table9 : absolute maximum rating parameter symbol rating unit ambient temperature (industrial) t a -25 ~ 85 c ambient temperature (commercial) 0 ~ 70 storage temperature t stg -55 ~ 150 c voltage on any pin relative to vss v in , v out -0.3 ~ 2.7 v voltage on vdd relative to vss vdd, vddq -0.3 ~ 2.7 v short circuit output current i os 50 ma power dissipation p d 0.7 w note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational s ections of this specification is not implied. exposure to absolute maximu m rating conditions for extended periods may affect reliability. table10 : dc operating condition (voltage referenced to vss=0v, t a = -25 ~ 85 c) note : 1. all voltages are referenced to vss = 0v 2. vdd and vddq must track each other, and vddq must not exceed the level of vdd parameter symbol min typ max unit note power supply voltage vdd 1.7 1.8 1.95 v 1 power supply voltage vddq 1.7 1.8 1.95 v 1,2 input high voltage v ih (dc) 0.7 x vddq vddq + 0.3 v input low voltage v il (dc) -0.3 0.3 x vddq v output high voltage v oh (dc) 0.9 x vddq - v i oh =-0.1ma output low voltage v ol (dc) - 0.1 x vddq v i ol =0.1ma input leakage current i li -2 2 ua output leakage current i lo -5 5 ua table11 : ac operating condition note : 1. the value of v ix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. parameter symbol min max unit note input high voltage, all inputs v ih (ac) 0.8 x vddq vddq + 0.3 v input low voltage, all inputs v il (ac) -0.3 0.2 x vddq v input crossing point volt age, ck and /ck inputs v ix 0.4 x vddq 0.6 x vddq v 1
advanced information is43lr16800e 22 table13 : ac operating test condition (t a = -25 ~ 85 c, vdd = 1.7v to 1.95v, vss=0v) parameter symbol value unit ac input high/low level voltage v ih / v il 0.8 x vddq / 0.2 x vddq v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timing measurement reference level voltage v outref 0.5 x vddq v output load capacitance for access time measurement c l 20 pf figure8 : output load circuit table12 : capacitance (t a =25 c, f=1mhz, vdd=1.8v) parameter pin symbol min max unit input capacitance ck, /ck c i1 1.5 3.5 pf a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we c i2 1.5 3.0 pf ldm, udm c i3 2 4.5 pf data & dqs input/output capacitance dq0~dq15, ldqs, udqs c io 2 4.5 pf table14 : ac overshoot/undershoot specification parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vdd/vddq 3v-ns maximum undershoot area below vss/vssq 3v-ns figure9 : ac overshoot/undershoot definition maximum amplitude vdd/vddq vss/vssq voltage [v] maximum amplitude time [ns] overshoot area undershoot area output 10.6k 13.9k vddq 20pf output 20pf 50 vtt=0.5 x vddq z0=50 dc output load circuit ac output load circuit
advanced information is43lr16800e 23 table15 : dc characteristic (dc operating conditions unless otherwise noted) note : 1. measured with outputs open. 2. refresh period is 64ms. parameter symbol test condition speed unit note -60 -75 -10 operating one bank active- precharge current idd0 trc = trc(min), tck = tck(min), cke is high, /cs is high between valid commands, address inputs are switching, data bus inputs are stable 55 50 45 ma 1 precharge power-down standby current idd2p all banks idle, cke is low, /cs is high, tck = tck(min), address and control inputs are switching, data bus inputs are stable 0.3 ma precharge power-down standby current with clock stop idd2ps all banks idle, cke is low, /cs is high, ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 0.3 ma precharge non power-down standby current idd2n all banks idle, cke is high, /cs is high, tck = tck(min) , address and control inputs are switching, data bus inputs are stable 9.0 ma precharge non power-down standby current with clock stop idd2ns all banks idle, cke is high, /cs is high, ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 5.0 ma active power-down standby current idd3p one bank active, cke is low, /cs is high, tck = tck(min), address and control inputs are switching, data bus inputs are stable 5.0 ma active power-down standby current with clock stop idd3ps one bank active, cke is low, /cs is high, ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 5.0 ma active non power-down standby current idd3n one bank active, cke is high, /cs is high, tck = tck(min), address and control inputs are switching, data bus inputs are stable 20 ma active non power-down standby current with clock stop idd3ns one bank active, cke is high, /cs is high, ck = low, /ck = high, address and control inputs are switching, data bus inputs are stable 10 ma operating burst read current idd4r one bank active, bl=4, cl=3, tck = tck(min), continuous read bursts, iout=0ma, address inputs are switching, 50% data change each burst transfer 90 80 70 ma 1 operating burst write current idd4w one bank active, bl=4, tck=tck(min), continuous write bursts, address inputs are switching, 50% data change each burst transfer 90 80 70 ma 1 auto refresh current idd5 trc=trfc(min), tck=tck(min), burst refresh, cke is high, address and control inputs are switching, data bus inputs are stable 90 ma 2 self refresh current pasr tcsr idd6 cke is low ck=low, /ck=high tck=tck(min) extended mode register set to all 0's, address and control inputs are stable, data bus inputs are stable ua 4 banks 85 c 350 45 c 300 2 banks 85 c 250 45 c 210 1 bank 85 c 200 45 c 170 half bank 85 c 175 45 c 155 quarter bank 85 c 165 45 c 150 standby current in deep power down mode idd8 address and control inputs are stable, data bus inputs are stable 30 ua
advanced information is43lr16800e 24 parameter symbol -60 -75 -10 unit note min max min max min max system clock cycle time cl=3 tck 6 7.5 10 ns 1 cl=2 10 10 10 ns 1 dq output access time from ck, /ck cl=3 tac 2.0 5.5 2.0 6.0 2.0 7.0 ns cl=2 2.0 8.0 2.0 8.0 2.0 8.0 clock high pulse width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low pulse width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck cke min. pulse width (high/low pulse width) tcke 1 1 1 tck dq and dm input setup time tds 0.6 0.9 1.2 ns 2, 3, 4 dq and dm input hold time tdh 0.6 0.9 1.2 ns 2, 3, 4 dq and dm input pulse width tdipw 1.8 2.0 2.4 ns 5 address and control input setup time tis 1.1 1.3 1.5 ns 4, 6, 7 address and control input hold time tih 1.1 1.3 1.5 ns 4, 6, 7 address and control input pulse width tipw 2.7 3.0 3.4 ns 5 dq & dqs low-impedance time from ck, /ck tlz 1.0 1.0 1.0 ns 8 dq & dqs high-impedance time from ck, /ck thz 5.5 6 7 ns 8 dqs - dq skew tdqsq 0.5 0.6 0.7 ns 9 half clock period thp tch, tcl tch, tcl tch, tcl ns data hold skew factor tqhs 0.65 0.75 1 ns dq / dqs output hold time from dqs tqh thp-tqhs thp-tqhs thp-tqhs ns write command to first dqs latching transition tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs input high pulse width tdqsh 0.35 0.6 0.4 0.6 0.4 0.6 tck dqs input low pulse width tdqsl 0.35 0.6 0.4 0.6 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 0.2 0.2 tck dqs falling edge hold time from ck tdsh 0.2 0.2 0.2 tck access window of dqs from ck, /ck cl=3 tdqsck 2.0 5.5 2.0 6.0 2.0 7.0 ns cl=2 2.0 8.0 2.0 8.0 2.0 8.0 ns active to precharge command period tras 42 45 50 ns active to active command period trc 60 75 80 ns mode register set command cycle time tmrd 2 2 2 tck refresh period tref 64 64 64 ms average periodic refresh interval trefi 15.6 15.6 15.6 us 10 auto refresh period trfc 70 70 70 ns active to read or write delay trcd 18 22.5 30 ns precharge command period trp 18 22.5 30 ns active bank a to active bank b delay trrd 12 15 15 ns write recovery time twr 12 15 15 ns auto precharge write recovery + precharge time tdal (twr/tck) + (trp/tck) internal write to read command delay twtr 1 1 1 tck dqs read preamble cl=3 trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck 11 cl=2 0.5 1.1 0.5 1.1 0.5 1.1 tck 11 dqs read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs write preamble twpre 0.25 0.25 0.25 tck dqs write preamble setup time twpres 0 0 0 ns 12 dqs write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 13 exit power down to next valid command delay txp 1 1 1 tck self refresh exit to next valid command delay txsr 120 120 120 ns table16: ac characteristic (ac operation conditions unless otherwise noted)
advanced information is43lr16800e 25 note : 1. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified fo r the clock pin) during access or precharge states (read, write, including tdpl, and precharge commands). cke may be used to reduce the data rate. 2. 4. the transition time for dq, dm and dqs inputs is measured between vil(dc) to vih(ac) for rising input signals, and vih(dc ) to vil(ac) for falling input signals. 3. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tran sitions through the dc region must be monotonic. 4. input slew rate 0.5v/ns and < 1.0v/ns. 5. these parameters guarantee device timing but they are not necessarily tested on each device. 6. the transition time for address and command inputs is measured between vih and vil. 7. a ck,/ck slew rate must be 1.0v/ns (2.0v/ns if measured different ially) is assumed for this parameter. 8. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referred t o a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 9. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for a ny given cycle. 10. a maximum of eight refresh commands can be posted to an y given low-power ddr sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 8*trefi. 11. a low level on dqs may be maintained during high-z states (d qs drivers disabled) by adding a weak pull-down element in the s ystem. it is recommended to turn off the weak pull-down elemen t during read and write bursts (dqs drivers enabled). 12. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meet ing the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transition ing from hi-z to logic low. if a previous write was in progress, dqs could be high, l ow, or transitioning from high to low at this time, depending on tdqss. 13. the maximum limit for this parameter is not a device limit. th e device operates with a greate r value for this parameter, bu t system performance (bus turnaround) will degrade accordingly. input setup/hold slew rate [v/ns]  tds/  tis [ps]  tdh/  tih [ps] 1.0 0 0 0.5 +150 +150 ck,/ck setup/hold slew rate [v/ns]  tds/  tis [ps]  tdh/  tih [ps] 1.0 0 0
advanced information is43lr16800e 26 timing diagram bank/row activation the active command is used to activate a row in particular bank for a subsequent read or write access. the value of the ba0,ba1 inputs selects the bank, and the address provided on a0-a 11(or the highest address bit) selects the row. before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be opened. this is accomplished via the active command, whic h selects both the bank and the row to be activated. the row remains active until a precharge (or read with auto precharge or write with auto precharge) command is issued to the bank. a precharge (or read with auto precharge or write with auto precharge) command must be issued before opening a different row in the same bank. figure11 : trcd, trrd, trc once a row is open(with an active command) a read or write comman d may be issued to that row, subject to the trcd specification. trcd(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge af ter the active command on which a read or write command can be entered. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been closed(precharge). the minimum time interval between successive active commands to the same bank is defined by trc. a subsequen t active command to another bank can be issued while the first ba nk is being accessed, which results in a reduction of total row- access overhead. the minimum time interval between successive ac tive commands to different banks is defined by trrd. figure10 : active command notes : 1. ra : row address 2. ba : bank address c l k / c l k cke / cs / ras / cas / we ra ba a 0 ~ a 11 ba 0 , ba 1 don ? t care rd / wt with ap act nop nop nop bank a row act nop / clk c l k c ommand t 0 t 1 t 2 t 3 a 0 - a 11 ba 0 , ba 1 col bank a t 4 t a 0 t a 1 t rcd don ? t care row bank b t rrd bank a row act t rc t a 2 tch tcl tis tih tc k
advanced information is43lr16800e 27 read the read command is used to initiate a burst read to an active row. the value of ba0 and ba1 se lects the bank and address inputs select the starting column location. the value of a10 determines whether or not auto-precharge is us ed. if auto-precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is no t selected, the row will remain op en for subsequent access. the v alid data- out elements will be available cas latency after the read command is issued. the mobile ddr drives the dqs during read operations. the initia l low state of the dqs is known as the read preamble and the la st data- out element is coincident with the read postamble. dqs is edge-ali gned with read data. upon completion of a burst, assuming no new read commands have been initiated, the i/o's will go high-z. figure12 : read command notes : 1. ca : column address 2. ba : bank address 3. a10=high : enable auto precharge a10=low : disable auto precharge figure13 : read data out timing (bl=4) notes: 1. bl=4 2. shown with nominal tac, tdqsck and tdqsq c l k / c l k cke / cs / ras / cas / we ca a 0 ~ a 8 a 10 ba ba 0 , ba 1 don ? t care bank a col n / c l k c l k c ommand t 0 t 1 t 2 t 3 t 1 n t 2 n t 3 n read nop nop nop dqs dq cl = 3 d out n + 1 trpre t 4 t 4 n nop trpst d out n d out n + 2 d out n + 3 don ? t care address tac tdqsck tqh tlz thz tdqsq dqs dq cl = 2 d out n + 1 d out n d out n + 2 d out n + 3 trpre tac trpst
advanced information is43lr16800e 28 figure14 : consecutive read bursts (bl=4) figure15 : non-consecutive read bursts (bl=4) notes: 1. dout n or m = data-out from column n or m 2. bl=4,8,16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3. shown with nominal tac, tdqsck and tdqsq notes: 1. dout n or m = data-out from column n or m 2. bl=4,8,16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first) 3. shown with nominal tac, tdqsck and tdqsq d out m bank a col m bank a col n nop read nop nop nop read t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dq cl = 3 command dqs don ? t care d out n + 1 d out n d out n + 2 d out n + 3 d out m + 1 bank a col m bank a col n nop read nop nop nop read t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dq cl = 3 command dqs don ? t care d out n + 1 d out n d out n + 2 d out n + 3 cl = 3 nop d out m d out m + 1
advanced information is43lr16800e 29 figure17 : read burst terminate (bl=4,8 or 16) truncated reads data from any read burst may be truncated with a burst te rminate command, as shown in figure16. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). data from any read burst must be completed or truncated befo re a subsequent write command can be issued. if truncation is necessary, the burst terminat e command must be used. a read burst may be followed by, or truncated with, a precharge co mmand to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles afte r the read command, where x equals the number of desired data element pairs (pairs are required by the n-prefetch architecture). this is shown in figure (read to precharge). following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. figure16 : random read access notes: 1. dout n or m,p,q = data-out from column n or m,p,q 2. bl=2,4,8,16 (if 4,8 or 16, the fo llowing burst interrupts the previous) 3. reads are to an active row in any bank. 4. shown with nominal tac, tdqsck and tdqsq notes: 1. dout n = data-out from column n 2. cke=high 3. shown with nominal tac, tdqsck and tdqsq bank a col m bank a col p d out p bank a col q bank a col n read read read nop nop read t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dq cl = 3 command dqs don ? t care d out n + 1 d out n d out m d out m + 1 nop d out q d out q + 1 d out p + 1 bank a col n nop read bst nop nop t 0 t 1 t 2 t 3 a ddress t 4 / clk clk dq cl = 3 command dqs don ? t care d out n + 1 d out n
advanced information is43lr16800e 30 figure19 : read to precharge (bl=4) figure18 : read to write terminate (bl=4,8 or 16) notes: 1. dout n = data-out from column n , din m = data-in from column m. 2. cke=high 3. shown with nominal tac, tdqsck and tdqsq notes: 1. dout n = data-out from column n. 2. read to precharge equals 2 tck, which allows 2 data pairs of data-out. 3. shown with nominal tac, tdqsck and tdqsq bank a col m nop bank a col n nop read bst write nop t 0 t 1 t 2 t 3 a ddress t 4 / clk clk dq cl = 3 command dqs don ? t care d out n + 1 d out n tdqss ( nom ) d in m d in m + 1 t 5 bank a ( a , or all ) bank a col n pcg read nop act nop nop t 0 t 1 t 2 t 3 address t 4 t 5 / clk clk dq cl = 3 command dqs bank a row trp don ? t care d out n + 1 d out n d out n + 2 d out n + 3
advanced information is43lr16800e 31 figure21 : write burst (bl=4) write the write command is used to initiate a burst write access to an active row. the value of ba0, ba1 selects the bank and address inputs select the starting column location. the value of a10 determines whether or not auto precharge is used.if autoprecharge is selected , the row being accessed will be precharged at the end of the write burst; if auto precharge is no t selected, the row will remain open for subsequent access. inpu t data appearing on the data bus, is written to the memory array subject to the dm input lo gic level appearing coincident with the dat a. if a given dm signal is registered low, the correspond ing data will be written to the memory; if the dm signal is registered high, the cor responding data-inputs will be ignored, and a write will not be executed to that byte/column location. the memory controller drives the dqs during write operations. the initial low state of the dqs is known as the write preamble and the low state following the last data-in element is write postamble. upon completion of a burst, assu ming no new commands have been initiated, the i/o's will stay high-z and any addition al input data will be ignored. figure20 : write command notes : 1. ca : column address 2. ba : bank address 3. a10=high : enable auto precharge a10=low : disable auto precharge notes: 1. din n = data-in from column n. c l k / c l k cke / cs / ras / cas / we ca a 0 ~ a 8 a 10 ba ba 0 , ba 1 don ? t care bank a col m bank a col n write nop write / c l k c l k t 0 t 1 t 2 t 3 t 1 n t 2 n dq tdqss twpst don ? t care dqs twpres twpre tdh tds d m d in n d in n + 1 d in n + 2 d in n + 3 a ddress command tdqsh
advanced information is43lr16800e 32 figure22 : consecutive write to write (bl=4) figure23 : non-consecutive write to write (bl=4) notes: 1. din n = data-in from column n. 2. each write command may be to any banks. notes: 1. din n = data-in from column n. 2. each write command may be to any banks. write write nop nop nop nop bank a col n d in m bank a col m t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 d in m + 1 d in m + 2 d in m + 3 don ? t care nop write nop nop write nop bank a col n d in m t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 d in m + 1 d in m + 2 d in m + 3 don ? t care bank a col m tdqss ( nom ) nop
advanced information is43lr16800e 33 figure24 : random write to write figure25 : write to read (uninterrupting) notes: 1. din n,p,m,q = data-in from column n,p,m,q. 2. each write command may be to any banks. notes: 1. din n = data-in from column n, dout m = data-out from column m. 2. twtr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different bank s, in which case twtr is not required and the read command could be applied ealier. d in q + 1 bank a col q bank a col p write write write write nop bank a col n d in m bank a col m t 0 t 1 t 2 t 3 a ddress t 4 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in p d in p + 1 d in m + 1 d in q don ? t care nop write bank a col m nop nop read nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 don ? t care cl = 3 nop nop d out m + 1 d out m t wtr d out m + 2 t 6 t 7
advanced information is43lr16800e 34 figure26 : write to read (interrupting) figure27 : write to read (odd number of data interrupting) notes: 1. din n = data-in from column n, dout m = data-out from column m. 2. twtr is referenced from the first positive ck edge after the last data-in pair. notes: 1. din n = data-in from column n, dout m = data-out from column m. 2. twtr is referenced from the first positive ck edge after the last data-in pair. write nop t 6 t 7 nop nop read nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 don ? t care bank a col m cl = 3 nop nop d out m + 1 d out m d out m + 2 d out m + 3 t wtr t 6 t 7 t 0 t 1 t 2 t 3 t 4 t 5 dqs dq tdqss ( nom ) dm d in n don ? t care cl = 3 d out m + 1 d out m d out m + 2 d out m + 3 t wtr write nop nop nop read nop bank a col n a ddress / clk clk command bank a col m nop nop
advanced information is43lr16800e 35 figure28 : write to precharge (uninterrupting) figure29 : write to precharge (interrupting) notes: 1. din n = data-in from column n. 2. twr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different ba nks, in which case twr is not required and the read command could be applied ealier. notes: 1. din n = data-in from column n. 2. twr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different ba nks, in which case twr is not required and the read command could be applied ealier. pcg nop write nop nop nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 d in n + 2 d in n + 3 don ? t care twr nop write nop nop pcg nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n d in n + 1 twr don ? t care
advanced information is43lr16800e 36 figure30 : write to precharge (odd number of data interrupting) notes: 1. din n = data-in from column n. 2. twr is referenced from the first positive ck edge after the last data-in pair. 3. read and write command can be directed to different ba nks, in which case twr is not required and the read command could be applied ealier. don ? t care nop write nop nop pcg nop bank a col n t 0 t 1 t 2 t 3 a ddress t 4 t 5 / clk clk dqs dq tdqss ( nom ) command dm d in n twr
advanced information is43lr16800e 37 precharge the precharge command is used to deactivate the open row in a part icular bank or the open row in al l banks. the banks will be ava ilable for subsequent row access some specified time (trp) after the precharge command issued. input a10 determines whether one or all banks are to be precharged . in the case where only one bank is to be precharged (a10=low ), inputs ba0,ba1 select the banks. when all banks are to be precharged (a10=high ), inputs ba0,ba1 are treated as a ?don?t care?. once a bank has been precharged, i t is in the idle state and must be actived prior to any re ad or write commands being issued to that bank. figure31 : precharge command notes : 1. ba : bank address mode register the mode register contains the specific mo de of operation of the mobile ddr sdram. th is register includes the selection of a burs t length ( 2, 4, 8, 16), a cas latency(2, 3), a burst type. the mode register set must be done before any activate command after the power up sequence. any contents of the mode register be alte red by re-programming the mode register thro ugh the execution of mode register set comm and. t ck 2 ck min 0 1 2 3 4 5 6 7 8 /clk clk 9 10 cmd t rp precharge all bank mode resister set command (any) figure32 : mode resister set c l k / c l k cke / cs / ras / cas / we ba a 10 ba 0 , ba 1 don ? t care
advanced information is43lr16800e 38 figure34 : self refresh self refresh this state retains data in the mobile ddr, even if the rest of the system is powered down (even without external clocking). note refresh interval timing while in self refresh mode is scheduled internally in the mobile ddr and may vary and may not meet trefi time. " don't care" except cke, which must rema in low. an internal refresh cycle is scheduled on self refresh entry. the procedure for exitin gself refresh mode requires a series of commands. first clock must be stable before cke goin g high. nop commands should be issued for the duration of the refresh exit time (txsr), because time is requir ed for the completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally timed eve nt can be missed when cke is raised for exit from self refre sh mode. figure33 : auto refresh auto refresh the auto refresh command is used during normal operation of the mo bile ddr. it is non persistent, so must be issued each time a refresh is required. the refresh addressing is gene rated by the internal refresh controller. th e mobile ddr requires auto refresh comman ds at an average periodic interval of trefi. to allow for improved effi ciency in scheduling and switchin g between tasks, some flexibilit y in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given mobile ddr, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8*trefi. aref nop nop nop aref pcg nop / c l k c l k cke t 0 c ommand t 1 t 3 tch tcl dqs , dq , dm tb 0 tis tih a 10 tc k t 2 t 4 ta 0 trp don ? t care valid a 0 ~ a 9 , a 11 all banks one bank ba ba 0 , ba 1 act nop tb 0 ra ta 2 ba ra nop valid trfc trfc tis tih valid nop aref nop / c l k c l k cke t 0 c ommand t 1 t a 0 dqs , dq , dm tb 0 tis tih t a 1 trp don ? t care address txsr tis tih tis tis valid self - refresh mode entry self - refresh mode exit
advanced information is43lr16800e 39 figure35 : power down (active or precharge) figure36 : deep power down power down power down occurs if cke is set low coincident with device dese lect or nop command and when no accesses are in progress. if po wer down occurs when all banks are idle, it is precharge power down. if power down occurs when one or more banks are active, it is r eferred to as active power down. the device cannot stay in this mode for longer than the refresh requirements of the device, without losin g data. the power down state is exited by setting cke high while issuing a device deselect or nop command. a valid command can be issued af ter txp. deep power down the deep power-down (dpd) mode enables very low standby currents . all internal voltage generators inside the mobile ddr are sto pped and all memory data is lost in this mode. all the information in the mode register and the extended mode register is lost. next figure, deep power-down command shows the deep power-down command all banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this state, cke must be held in a constant low state. to exit the dpd mode, cke is taken high a fter the clock is stable and nop command must be maintained for at least 200 us. valid nop nop valid / c l k c l k cke t 0 c ommand t 1 ta 0 tch tcl dqs , dq , dm tis tih valid address tc k valid tis tis tih tis tih t 2 ta 1 tb 0 must not exceed refresh device limits don ? t care power - down mode entry power - down mode exit t xp valid nop nop dpd nop / c l k c l k cke t 0 c ommand t 1 ta 0 dqs , dq , dm tb 0 address tc ke valid tis t 2 ta 1 ta 2 don ? t care deep power - down mode entry deep power - down mode exit t = 200 us
advanced information is43lr16800e 40 clock stop mode clock stop mode is a feature supported by mobile ddr sdram devi ces. it reduces clock-related po wer consumption during idle periods of the device. conditions: the mobile ddr sdram supports clock stop in case: ? the last access command (active, read, write, precharge, au to refresh or mode register set) has executed to completion, including any data-out during read bursts; the number of required clock pulses per access command depends on the device's ac tim ing parameters and the clock frequency; ? the related timing condition (trcd, twr, trp, trfc, tmrd) has been met; ?cke is held high . when all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with ck held low and /ck held high. clock stop mode is ex ited when the clock is restarted. nops comm and have to be issued for at least one clo ck cycle before the next access comm and may be applied. additional clock pulses might be required depending on the system character istics. figure37 illustrates the clock stop mode: ? initially the device is in clock stop mode; ? the clock is restarted with the rising e dge of t0 and a nop on the command inputs; ? with t1 a valid access command is latched; this command is follo wed by nop commands in order to allow for clock stop as soon as this access command has completed; ?t n is the last clock pulse required by the access command latched with t1. ? the timing condition of this access command is met with the completion of t n ; therefore tn is the last cl ock pulse required by this command and the clock is then stopped. figure 37 : clock stop mode dq,dqs (high ? z) exit clock stop mode enter clock stop mode vail command cke t0 t1 t2 t n /clk clk add timing condition cmd clock stopped don?t care nop cmd nop nop nop valide high
advanced information is43lr16800e 41 figure38 : 60ball fbga configuration note: all dimensions in millimeters [bottom view] 9 8 7 6 5 4 3 2 1 0.80 6.4 10.0 0.1 8.0 0.1 7.2 1.1max 0.35 0.05 0.45 0.05 unit [mm] a b c d e f g h j k 0.80 0.8
advanced information is43lr16800e 42 configuration frequency (mhz) speed (ns) order part no. package 8mx16 166 6 IS43LR16800E-6BLE 60-ball bga, lead-free 133 7.5 is43lr16800e-75ble 60-ball bga, lead-free ordering information ? vdd = 1.8v extended range: (-25 o c to +85 o c)


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